1. Field of the Invention
The present invention is related to a method for reading a memory array with a non-volatile memory structure, and more particularly, to a method for reading a memory array of a symmetrical and self-aligned non-volatile memory structure with a high cell density and an improved coupling ratio.
2. Description of the Prior Art
Erasable programmable read only memories (EPROMs) and electrically erasable programmable read only memories (EEPROMs) are well known non-volatile memory devices capable of storing data, as well as erasing and rewriting data, as desired.
The conventional non-volatile memory cells normally need high currents to operate, e.g., 200 microamperes (μA), for hot electron programming, and are not suitable for low-power devices that are currently the trend of chip development. Therefore, one form of an EEPROM device includes a so-called “split-gate” electrode that has been developed to obtain high efficiency and low current programming, where the programming current can be diminished to, for example, 1 μA.
Many EEPROM devices use two polysilicon layers (one for the formation of the floating gate and another for the formation of the control gate and possible electrical interconnects) whereas other EEPROM devices use three polysilicon layers. For example, U.S. Pat. No. 4,302,766 provides a first polysilicon layer serving as the floating gate, a second polysilicon layer serving as the control gate, and a third polysilicon layer coupled through an erase window to a portion of the first polysilicon layer for use during erasure of the cell. U.S. Pat. No. 4,331,968 also uses a third layer of polysilicon to form an erase gate, and U.S. Pat. Nos. 4,561,004 and 4,803,529 use three polysilicon layers in their own specific configurations.
U.S. Pat. No. 4,622,656 describes an EEPROM device in which a reduced programming voltage is provided by having a highly doped channel region under the select gate, and having the channel region under the floating gate being either lightly doped or doped to the opposite conductivity type, thereby providing a significant surface potential gap at the transition location of the channel.
U.S. Pat. No. 5,712,180 discloses a flash EEPROM cell layout as shown in FIG. 1, and the cross-sectional diagram of line A-A in FIG. 1 is shown in FIG. 2. EEPROM cell 101 includes a buried source region 102 and a buried drain region 103, each being buried by a relatively thick layer of dielectric 104 and 105, respectively. Channel region 106 is divided into a first portion 106-1 and a second portion 106-2. The first portion 106-1 is influenced by the polysilicon layer 109 and serves as a select gate, whereas the second portion 106-2 is influenced by a floating gate 107 formed of a polysilicon layer and which, in turn, is influenced by control gate 108 formed of a polysilicon layer. As is well known in the art, suitable dielectric layers such as thermally grown oxide are located between channel 106, polysilicon layer 109, and polysilicon layer 107 for insulation. Similarly, suitable dielectric layers such as oxide or composite oxide/nitride are formed between the three layers of polysilicon. Metal silicide can be used in place of one or more of the polysilicon layers 108 and 109. If desired, a highly-doped P+ region 120 is used within channel 106-2 adjacent to buried drain region 103, so as to provide a stable threshold voltage of the memory transistor including channel 106-2.
U.S. Pat. No. 5,414,693 also discloses a flash EEPROM memory structure as shown in FIG. 3. The cell structure is formed in a P-doped substrate 206 with a drain 204 of a transistor 201 and a drain 205 of a transistor 202. The drains 204 and 205 serve as bit lines. The transistor 201 includes a floating gate 207a and an overlying control gate 208a. Likewise, the transistor 202 includes a floating gate 207b and a control gate 208b located thereon. A word line 209 extends over the two transistors 201 and 202 and forms the control gate 209a of the select gate between the floating gate transistors 201 and 202. The word line 209 serially connects the select gates in one row of a memory array and runs perpendicular to the bit lines in columns, i.e., the drains 204 and 205.
To sum up, the floating gates in U.S. Pat. No. 5,712,180 and U.S. Pat. No. 5,414,693 are completely defined by the control gates during control gate patterning, so the floating gates have to be larger than the select gate in width direction to allow alignment tolerance. Under such circumstances, the memory cell size could not be reduced significantly.